A processor performing fetch or decoding of different instruction during the execution of another instruction is called ______
1.Super-scaling
2.Pipe-lining
3.Parallel Computation
4.None of the mentioned
A source program is usually in _______
1.Assembly language
2.Machine level language
3.High-level language
4.Natural language
An optimizing Compiler does _________
1.Better compilation of the given piece of code
2.Takes advantage of the type of processor and reduces its process time
3.Does better memory management
4.None of the mentioned
ANSI stands for __________
1.American National Standards Institute
2.American National Standard Interface
3.American Network Standard Interfacing
4.American Network Security Interrupt
As of 2000, the reference system to find the performance of a system is _____
1.Ultra SPARC 10
2.SUN SPARC
3.SUN II
4.None of the mentioned
As of 2000, the reference system to find the SPEC rating are built with _____ Processor.
1.Intel Atom SParc 300Mhz
2.Ultra SPARC -IIi 300MHZ
3.Amd Neutrino series
4.ASUS A series 450 Mhz
 IBM developed a bus standard for their line of computers ‘PC AT’ called _____
1. IB bus
2.M-bus
3. ISA
4.None of the mentioned
 The ALU makes use of _______ to store the intermediate results.
1.Accumulators
2.Registers
3. Heap
4.Stack
 The Input devices can send information to the processor.
1.When the SIN status flag is set
2.When the data arrives regardless of the SIN flag
3.Neither of the cases
4.Either of the cases
 The instruction -> Add LOCA, R0 does _______
1.Adds the value of LOCA to R0 and stores in the temp register
2.Adds the value of R0 to the address of LOCA
3.Adds the values of both LOCA and R0 and stores it in R0
4.Adds the value of LOCA with a value in accumulator and stores it in R0
 To extend the connectivity of the processor bus we use ________
1. PCI bus
2. SCSI bus
3.Controllers
4.Multiple bus
 Which registers can interact with the secondary storage?
1. MAR
2.PC
3.IR
4.R0
CISC stands for _______
1.Complete Instruction Sequential Compilation
2.Computer Integrated Sequential Compiler
3.Complex Instruction Set Computer
4.Complex Instruction Sequential Compilation
During the execution of a program which gets initialized first?
1.MDR
2.IR
3.PC
4.MAR
During the execution of the instructions, a copy of the instructions is placed in the ______
1.Register
2.RAM
3. System heap
4.Cache
For a given FINITE number of instructions to be executed, which architecture of the processor provides for a faster execution?
1.ISA
2.ANSA
3.Super-scalar
4.All of the mentioned
If the instruction, Add R1, R2, R3 is executed in a system that is pipe-lined, then the value of S is (Where S is a term of the Basic performance equation)?
1.3
2. ~2
3. ~1
4.6
In multiple Bus organisation, the registers are collectively placed and referred as ______
1.Set registers
2.Register file
3.Register Block
4.Map registers
ISP stands for _________
1.Instruction Set Processor
2.Information Standard Processing
3.Interchange Standard Protocol
4.Interrupt Service Procedure
The ______ format is usually used to store data.
1.BCD
2.Decimal
3.Hexadecimal
4.Octal
MFC stands for ___________
1.Memory Format Caches
2.Memory Function Complete
3.Memory Find Command
4.Mass Format Command
SPEC stands for _______
1.Standard Performance Evaluation Code
2.System Processing Enhancing Code
3.System Performance Evaluation Corporation
4. Standard Processing Enhancement Corporation
The 8-bit encoding format used to store data in a computer is ______
1. ASCII
2.EBCDIC
3.ANCI
4.USCII
The average number of steps taken to execute the set of instructions can be made to be less than one by following _______
1. ISA
2. Pipe-lining
3.Super-scaling
4. Sequential
The bus used to connect the monitor to the CPU is ______
1.PCI bus
2.SCSI bus
3.Memory bus
4.Rambus
The clock rate of the processor can be improved by _________
1.Improving the IC technology of the logic circuits
2.Reducing the amount of processing done in one step
3.By using the overclocking method
4.All of the mentioned
The control unit controls other units by generating ________
1.Control signals
2.Timing signals
3.Transfer signals
4.Command Signals
The decoded instruction is stored in ______
1.IR
2.PC
3.Registers
4.MDR
The I/O interface required to connect the I/O device to the bus consists of ______
1. Address decoder and registers
2.Control circuits
3. Address decoder, registers and Control circuits
4.Only Control circuits
The internal components of the processor are connected by _______
1.Processor intra-connectivity circuitry
2.Processor bus
3.Memory bus
4.Rambus
The ISA standard Buses are used to connect ________
1.RAM and processor
2.GPU and processor
3.Harddisk and Processor
4.CD/DVD drives and Processor
The main advantage of multiple bus organisation over a single bus is _____
1.Reduction in the number of cycles for execution
2.Increase in size of the registers
3.Better Connectivity
4.None of the mentioned
The main virtue for using single Bus structure is ____________
1.Fast data transfers
2.Cost effective connectivity and speed
3.Cost effective connectivity and ease of attaching peripheral devices
4.None of the mentioned
The registers, ALU and the interconnection between them are collectively called as _____
1.process route
2.information trail
3.information path
4.data path
The small extremely fast, RAM’s are called as _______
1.Cache
2. Heaps
3.Accumulators
4.Stacks
The time delay between two successive initiations of memory operation _______
1.Memory access time
2.Memory search time
3. Memory cycle time
4.Instruction delay
The ultimate goal of a compiler is to ________
1.Reduce the clock cycles for a programming task
2.Reduce the size of the object code
3.Be versatile
4.Be able to detect even the smallest of errors
To reduce the memory access time we generally make use of ______
1. Heaps
2. Higher capacity RAM’s
3.SDRAM’s
4.Cache’s
Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an average of 3 steps and B can execute with an average of 5 steps. For the execution of the same instruction which processor is faster?
1.A
2.B
3.Both take the same time
4. Insufficient information
When Performing a looping operation, the instruction gets stored in the ______
1.Registers
2.Cache
3.System Heap
4.System stack
Which memory device is generally made of semiconductors?
1.RAM
2.Hard-disk
3. Floppy disk
4. Cd disk
Which of the register/s of the processor is/are connected to Memory Bus?
1.PC
2.MAR
3.IR
4.Both PC and MAR
___ register Connected to the Processor bus is a single-way transfer capable.
1. PC
2.IR
3.Temp
4. Z
_____ are used to overcome the difference in data transfer speeds of various devices.
1. Speed enhancing circuitory
2.Bridge circuits
3.Multiple Buses
4.Buffer registers
_____ bus structure is usually used to connect I/O devices.
1.Single bus
2.Single bus
3. Star bus
4.Rambus
_____ is generally used to increase the apparent size of physical memory.
1.Secondary memory
2.Virtual memory
3. Hard-disk
4.Disks
_____ is used to choose between incrementing the PC or performing ALU operations.
1.Conditional codes
2.Multiplexer
3.Control unit
4.None of the mentioned
______ are numbers and encoded characters, generally used as operands.
1.Input
2.Data
3.Information
4.Stored Values
_______ is used to store data in registers.
1. D flip flop
2.JK flip flop
3.RS flip flop
4.None of the mentioned